Lattice-based Quantum-resistant Algorithm & Chip Fits IoT Nodes

Lattice-based Quantum-resistant Algorithm & Chip Fits IoT Nodes. 
Engineers from MIT have reported the creation of an encryption system that performs one of the U.S. National Institute of Standards and Technology (NIST) quantum-resistant algorithms currently under study.  Further, the algorithm is contained in “a chip small enough and energy-efficient enough to guard battery-powered nodes on the Internet of Things from future quantum attack.”

“The MIT engineers focused on one family of post-quantum algorithms, called lattice-based cryptography.  The name comes from a way to picture the problems that would need to be solved to crack this kind of encryption.  Imagine a two-dimensional grid with points scattered around it.  It might not seem too difficult to find the shortest vector between a random spot on the lattice and the nearest point, but expand the grid into three dimensions, and then 1,000, and then 10,000, and it becomes enough to occupy today’s computers for years.”

The MIT team’s next goal is ensuring the data processed in the chip is not-susceptible to side-channel and other computing attacks.  Side-channel attacks are ways to steal data indirectly through things such as changes in a chip’s power consumption, how it radiates energy, or how long certain actions take.  Other attacks involving processor timing are under study.

Reference is found at IEEE Spectrum…

Additional reference found at the 2019 International Solid-State Circuits Conference…


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